Projects

Fast Track: High Frame Rate Stereovision Tracking System

Funded by:

Period of R&D:

Summary of the project:

The project is associated with investigation and development of space-borne computer stereovision system for automated satellite grasping and automated satellite docking for recent space robotic systems developed at MDA Space Missions. The ERSL component of the R&D is associated with development of application specific (200 frames per second) stereo video sensors with on-board preprocessing FPGA-based reconfigurable multi-stream platform and implementation of stereovision tracking algorithms on the FPGA based computing platform.

FPGA based Stream Processing Platform with Temporal Partitioning Mechanism

Funded by:

Period of R&D:

November, 2005 to November, 2006

Summary of the project:

The prototype of the platform for the new generation of Multimedia, DVB (Digital Video Broadcasting) and DAB (Digital Audio Broadcasting) systems has been developed. The architecture of the platform is based on the concept of run-time temporal partitioning of FPGA on-chip resources and allocation of stream processing task macro-operators sequentially in the FPGA based multi-stream processor. This concept has been proposed and developed in the ERSL and presented in the Conference AMT2005 – Advanced Manufacturing Technologies with demonstration of the first prototype based on Xilinx Virtex II FPGA (presented below). The current platform has been developed on the basis of recent Xilinx Virtex-4 FPGA. First prototype of the platform which utilize the concept of run-time temporal partitioning mechanism (TPM).  

Research and Development of Adaptive Group Organized Reconfigurable Architecture (AGORA) Parallel Computing Platform for Data-Flow Tasks

Funded by:

Period of R&D:

May, 2001 to November, 2005

Summary of the project:

The concept of the Run -Time Re-configurable (RTR) parallel computing platform with Adaptive Group Organized Reconfigurable Architecture - AGORA was created based on the partially re-configurable Xilinx Virtex-E FPGA devices. The architecture of major components of the AGORA was developed. The concept of FPGA-frame based Virtual Hardware Components with self-assembling abilities was proposed and developed. The organization of Hardware Operating System (HOS) was developed prototyped and tested. A special software tool for partial reconfiguration of the Virtex-E based Reconfigurable Processing Module was developed implemented and tested. Recently, multi-stream parallel video-processor was implemented on the base of AGORA platform incorporated with the first embedded core of network processing module. New technology of self-assembling Virtual Hardware Components (VHC) was created, implemented and tested. Results of experiments based on created concepts and technologies were presented and published in proceedings of 2 Journals, 6 international conferences and technical reports. Parallel run-time reconfigurable computing platform with Adaptive Group Organized Reconfigurable Architecture (AGORA)

Development and Manufacturing of Reconfigurable Computing Module (RCM) for High Performance Data Stream Processing

Funded by:

Materials and Manufacturing of Ontario

Period of R&D:

July, 2001 to March 2003

Summary of the project:

Research and development of architecture organization for RCM was completed. This is the first prototype of partially reconfigurable computing module with parallel configuration of On-Chip micro-architecture. RCM was manufactured, tested and integrated later as a major functional component (Reconfigurable Functional Module – RFM) to the multi-task reconfigurable computing platform (see below project AGORA: Adaptive Group Organized Reconfigurable Architecture). Reconfigurable Computing Module (RCM)

Reconfigurable Parallel Computer System with Adaptation on Processing Tasks

Funded by:

NSERC

Period of R&D:

May, 1999 to May 2001

Summary of the project:

First complete prototype of Adaptive Reconfigurable Group Organized (ARGO) parallel computing system was developed, built and tested. New method for automated architecture synthesis of multi-mode, data-flow parallel computer systems was developed and partially tested on ARGO-platform.

Reconfigurable FPGA-based Processing Module with Adaptation on Processing Tasks

Funded by:

Ryerson University

Period of R&D:

September, 1999 to November, 2001

Summary of the project:

Two prototype modules based on XILINX “Spartan II” FPGA-family (First prototype) and XILINX “Vertex-E” FPGA-family (Second prototype) with parallel reconfiguration were developed, tested and implemented as a basic module for ARGO parallel computing system. New algorithms for run-time reconfiguration were developed and presented in conferences.

ERSL (c) 2007 | Updated March, 2007